1. Field of the Invention
This invention relates to an improvement in so-called “strained silicon” or “band engineered transistor” technology, and encompasses heterojunction field effect transistors fabricated with silicon-germanium and silicon-carbon alloys.
2. Description of the Related Art
In the current evolution of semiconductor devices, the limits of traditional scalability of CMOS transistors are rapidly being approached. This circumstance in turn has motivated increasing focus on three major groups of new transistors for the future—ultra-thin body silicon-on-insulator (SOI) transistors, band-engineered transistors and double-gate transistors.
Ultra-thin SOI transistors are made in very thin films of silicon about 100-250 Angstroms in thickness.
Band-engineered transistors are based on the approach of using new or modified materials for CMOS devices so that electrons move faster through the structure, such as by use of germanium and induction of mechanical stress in the structure to artificially control and improve transistor performance.
Double-gate transistors involve several potential approaches, including “fin FET” and vertical transistor designs, in which one gate is placed at the top of the transistor structure and another gate is placed on the bottom portion of the transistor. Such approach holds the potential to reduce transistor gate lengths to dimensions as small as 9 nanometers (nm), a current goal in the 22-nm node set for 2016. At 9 nm, gate structures will only be on the order of 30 atoms in length.
Considering the foregoing transistor types, anticipated challenges associated with ultra-thin SOI transistors and with double-gate transistors implicate band-engineered transistors as leading candidates for high-performance CMOS transistor development in the near term.
A simple version of band-engineered transistor is shown in the photomicrograph of FIG. 1. As labeled in the photomicrograph, the poly gate is positioned in the center of the structure, with a strained-silicon channel underneath the gate. The source and drain elements are to the left and right, respectively, in relation to the gate, and the strained silicon is formed by growth on a strain-relaxed Si0.85Ge0.15 layer, as a SiGe “virtual substrate.”
Such band-engineered transistor structures are more generally referred to as heterojunction field effect transistors (HFETs), and achieve mobility enhancement of charge carriers in operation by the presence of strain in the silicon layer. This charge carrier mobility enhancement is more significant for electrons than for holes. Mobility enhancements of 80% for NMOS HFET structures and 60% for PMOS HFET structures have been reported for strained silicon on Si0.7Ge0.3 (Currie, M., et al., JVST B19, 2268 (2001).
In such band-engineered HFET devices, the strained silicon layers are grown on strain-relaxed SiGe, which in turn is grown on silicon wafers. The strain-relaxed SiGe, commonly referred to as a SiGe relaxed buffer layer (RBL), is used as a “virtual substrate” for the silicon layer in this structural arrangement. RBLs and strained channel layers have been grown by molecular beam epitaxy (MBE) as well as chemical vapor deposition (CVD). Strained Si-channel layers, also termed quantum wells, are typically about 100-250 Angstroms in thickness.
FIG. 2 shows a cross-sectional tunneling electron microscope (TEM) image of a SiGe relaxed buffer layer structure. The compositionally graded layer is seen in the image to be a region of high dislocation density, with a low defect density material above it formed by the constant-Ge-composition “cap” layer of the RBL. In the field of view shown in the image, one threading dislocation is seen to extend up to the surface of the RBL.
In general, RBLs have three major requirements. They must have sufficient germanium content, often with a mole fraction of Ge in a range of 0.15-0.3, in the capping layer. The capping layer nominally is on the order of 1 micrometer (μm) in thickness. Second, RBLs must have the lowest defect density possible in the capping material. Third, the RBL structure must have a sufficiently smooth film for photolithographic processing after strained silicon growth.
In the fabrication of strained silicon growth structures, defects form as a result of a 4% difference in lattice constants between Si and Ge during the growth of Ge-containing layers on silicon. The associated inherent strain will produce misfit dislocations at sufficient thickness of the Ge-containing layer. The current state of the art is able to achieve a threading misfit dislocation density level just below 1×105 defects per square centimeter (cm2) for an illustrative 30% RBL (containing Si0.7Geo0.3).
One of the limitations of using SiGe for fabricating RBLs is the requirement of a high germanium content in the relaxed buffer layer (involving a mole fraction of Ge, as mentioned, that is typically in the range of 0.15 to 0.30), in order to achieve sufficient strain and consequent band-bending in the silicon channel. Since threading dislocation density and surface roughness of RBLs increase with increasing germanium content, it would be desirable to minimize Ge content in the RBL structure, but without the loss of performance that reduction of Ge-content in the RBL layer otherwise entails.